Clock distribution or the generation of multiple clocks is becoming more and more common in multi-processors, multi-channel high-speed transceivers, and many other types of synchronous systems. For example, some recent multi-lane transceivers operate at 25 gigabits/sec and above per lane of the transceiver, resulting in the transceivers having clocks operating at 25 gigahertz or more in each lane of the transceivers for a full-rate architecture, or 12.5 Ghz or more for a half-rate architecture. The power to distribute or generate clocks operating at these frequencies for each lane is consuming a larger portion of the total power of these transceivers. Furthermore, controlling jitter on distributed clocks operating at 25 gigahertz and higher is becoming increasingly difficult.
Current methods of distributing clocks to each lane of a transceiver include a central phase-locked-loop (PLL) that generates one clock and repeaters that distribute the clocks to other lanes. These repeaters typically are power hungry, create duty cycle distortion, and jitter. Alternately or additionally, a PLL may be included in each lane to generate a clock for each lane of a transceiver. However, having a PLL in each lane may result in high power consumption and large area overhead.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.